Various techniques of forming a bipolar element and an MOS element on the same semiconductor substrate have long been attempted, but when high-speed LSI circuits are desired, these techniques have several problems that are still not solved. The problems in the prior art will now be described.
FIG. 1 is a section through the structure of a typical conventional BiCMOS semiconductor device. An n-type buried layer 2 and n-type epitaxial layers 3 and 3' are formed on a p-type substrate 1. A vertical NPN bipolar transistor is formed so that its base 11 and emitter 12 are formed within the epitaxial layer 3' over the buried layer 2. A PMOS field-effect transistor (hereinafter simply called a "PMOS") is formed by forming a gate oxide film 7, a polycrystalline silicon gate 8 and a source and drain 10 within a n-type epitaxial layer 3. An NMOS field-effect transistor (hereinafter simply called an "NMOS") consists of a gate oxide film 7', a gate polycrystalline silicon 8' and source and drain 9 inside a p-type well 5. Reference numeral 4 denotes a p-type device-isolation region which isolates the bipolar element from the PMOS.
In this structure, the impurity concentration in the n-type epitaxial layers 3 and 3' is usually controlled to be at most 10.sup.16 /cm.sup.3, in order to control the threshold voltage of the PMOS. For this reason, the epitaxial layer 3 must be at least 4 .mu.m thick in order to insure the punch-through voltage (e.g., at least 10V) between the source and drain 10 of the PMOS and the p-type substrate 1. This means that the device-isolation region 4 must also be at least 4 .mu.m depth, and the width of this region 4 raises one of the problems preventing a high integration density. If a 5 .mu.m depth isolation layer is formed, for example, the width of the isolation layer is at least 10 .mu.m, including its spreading in the lateral direction.
As described above, in the conventional structure shown in FIG. 1, the epitaxial layers 3 and 3' must be thick, so that the width of the device-isolation region is also large, raising a problem when increasing the integration density.
FIG. 2 illustrates a prior-art technique which solves this problem ("BiMOS-A New Way to Simplify High Power Custom Interface", M. Heisig, IEEE, 1981).
The reference numerals in FIG. 2 have the same meaning as those in FIG. 1. The novel points of the structure of FIG. 2 compared with that of FIG. 1 are as follows.
(1) An n-type buried layer 2, which is the same as that below the bipolar element such as a bipolar transistor, is also formed below the PMOS. The buried layer 2 has an impurity concentration which is at least three orders of magnitude greater than that of the epitaxial layer 3, so that the punch-through described earlier does not occur, even when the thickness of the epitaxial layer 3 is reduced (e.g. to 2 .mu.m thick).
(2) P-type buried layers 14 and 14' are formed below the NMOS and in the device-isolation region, respectively, with the p-type wells 5 and 5' on top, to form a p-type well region and a device-isolation region, respectively. As a result, deep diffusion is not necessary to provide device-isolation, and the width of the device-isolation region can be reduced to less than 7 .mu.m, for instance.
As described above, the structure of FIG. 2 can realize a high density integration, but the following problems have yet to be solved in order to improve the MOS transistor performance as much as possible. When the n-type buried layers 2, 2' and the n-type epitaxial layers 3, 3' are used in common, the high-frequency characteristic (current gain bandwidth product f.sub.T) of the bipolar device increases as the thickness of the epitaxial layer decreases, but the increase in the junction capacity of the MOS transistor reduces the operational speed of the CMOS circuit.
In order to explain this problem in detail, FIG. 4 shows an example of the impurity concentration distribution in the bipolar transistor portion and the PMOS portion, and FIG. 5 shows the relationship between f.sub.T of the bipolar element and the ratio of increase in the junction capacity of the PMOS, with the abscissa denoting the thickness of the epitaxial layers 3 and 3'. The thinner the epitaxial layer 3', the greater becomes f.sub.T because the time taken for the carriers to travel through the low-concentration collector layer occupies the major proportion thereof, beside the time taken for the carriers to travel through the base layer. On the other hand, the capacity of the junction between the source and drain of the PMOS (for a 5V reverse bias) increases rapidly when the thickness of the epitaxial layer 3 is less than 3 .mu.m, for example, compared with the capacity C.sub.o when there is no n-type buried layer 2.
In the NMOS of FIG. 2, since the high concentration p-type buried layer 14 is formed on the substrate side thereof, the problem that a decrease in the thickness of the epitaxial layers 3, 3' results in an increase in the junction capacity occurs in the same way as in the PMOS.
As described above, the thickness of the epitaxial layers affects the performance of a bipolar element and that of a MOS transistor in opposite ways, and the prior-art technique has failed to solve this problem.
Recently, the gate length of MOS transistors has been reduced, because of the high-speed operation and the high integration density thereof. The problem in this case is that if the gate length is less than 2 .mu.m, for example, the threshold voltage of the element drops dramatically because of a short-channel effect. To counteract this short-channel effect, a well structure called a "retrograde well", in which the concentration is higher at a portion further from the surface, has been proposed. In order to counteract the short-channel effect, however, the depth to the high-concentration layer must be less than 1 .mu.m, and this can raise the problem of the increase of a source-drain capacitance.